Parallel Processing (cont’d)

Parallel Processing (cont’d)

• A serial-to-parallel converter
• A parallel-to-serial converter
D D x(n) D
T/4 T/4 T/4
T T T T
4k+3
x(4k+3) x(4k+2) x(4k+1) x(4k)
Sample Period T/4
D D D
T/4 T/4 T/4
T T T T
4k
y(4k+3) y(4k+2) y(4k+1) y(4k)
0 y(n)
Parallel Processing (cont’d)
• Why use parallel processing when pipelining can be used equally well?
– Consider the following chip set, when the critical path is less than the I/O
bound (output-pad delay plus input-pad delay and the wire delay between
the two chips), we say this system is communication bounded
– So, we know that pipelining can be used only to the extent such that the
critical path computation time is limited by the communication (or I/O)
bound. Once this is reached, pipelining can no longer increase the speed

Parallel Processing (cont’d)
– So, in such cases, pipelining can be combined with parallel processing to
further increase the speed of the DSP system
– By combining parallel processing (block size: L) and pipelining
(pipelining stage: M), the sample period can be reduce to:
– Example: (p.73, Fig.3.15 ) Pipelining plus parallel processing Example
(see the next page)
– Parallel processing can also be used for reduction of power consumption
while using slow clocks
L M
T T Tclock
iteration sample ⋅
= =

Parallel Processing (cont’d)
Example:Combined fine-grain pipelining and parallel processing
for 3-tap FIR filter

Pipelining and Parallel Processing for Low Power
• Two main advantages of using pipelining and parallel processing:
– Higher speed and Lower power consumption
• When sample speed does not need to be increased, these techniques
can be used for lowering the power consumption
• Two important formulas:
– Computing the propagation delay Tpd of CMOS circuit
– Computing the power consumption in CMOS circuit
2
0
arg 0
( ) t
ch e
pd k V V
C V
T
−
⋅
=
P C V f CMOS total = ⋅ 2 ⋅
0
Ccharge: the capacitance to be
charged or discharged in a
single clock cycle
Ctotal: the total capacitance
of the CMOS circuit

Pipelining and Parallel Processing for Low Power (cont’d)
• Pipelining for Lower Power
– The power consumption in the original sequential FIR filter
– For a M-level pipelined system, its critical path is reduced to 1/M of its
original length, and the capacitance to be charged/discharged in a single
clock cycle is also reduced to 1/M of its original capacitance
– If the same clock speed (clock frequency f) is maintained, only a fraction
(1/M) of the original capacitance is charged/discharged in the same
amount of time. This implies that the supply voltage can be reduced to
βVo (0<β <1). Hence, the power consumption of the pipelined filter is:
seq total seq P C V 2 f , f 1 T
0 = ⋅ ⋅ = Tseq: the clock period of the
original sequential FIR filter
pip total seq P = C ⋅ ⋅V 2 ⋅ f = 2 ⋅P
0
β 2 β

Pipelining and Parallel Processing for Low Power (cont’d)
– The power consumption of the pipelined system, compared with the
original system, is reduced by a factor of
– How to determine the power consumption reduction factor β?
• Using the relationship between the propagation delay of the original
filter and the pipelined filter
β 2
seq T
seq T seq T seq T
Sequential (critical path):
Pipelined: (critical path when M=3)
( ) 0 V
( )0 βV

Pipelining and Parallel Processing for Low Power (cont’d)
• The propagation delays of the original sequential filter and the
pipelined FIR filter are:
• Since the same clock speed is maintained in both filters, we get the
equation to solve β:
• Example: Please read textbook for Example 3.4.1 (pp.75)
2
0
arg 0
2
0
arg 0
( )
( )
,
( ) t
ch e
pip
t
ch e
seq k V V
C M V
T
k V V
C V
T
−
⋅
=
−
⋅
=
β
β
2
0
2
0 ( ) ( ) t t M βV −V = β V −V

Pipelining and Parallel Processing for Low Power (cont’d)
• Parallel Processing for Low Power
– In an L-parallel system, the charging capacitance does not change, but the
total capacitance is increased by L times
– In order to maintain the same sample rate, the clock period of the Lparallel
circuit is increased to LTseq (where Tseq is the propagation delay
of the original sequential circuit).
– This means that the charging capacitance is charged/discharged L times
longer (i.e., LTseq). In other words, the supply voltage can be reduced to
βVo since there is more time to charge the same capacitance
– How to get the power consumption reduction factor β?
• The propagation delay consideration can again be used to compute β
(Please see the next page)

Pipelining and Parallel Processing for Low Power (cont’d)
• The propagation delay of the original system is still same, but the
propagation delay of the L-parallel system is given by
seq T
seq 3T
seq 3T
seq 3T
Sequential(critical path):
Parallel: (critical path when L=3)
( ) 0 V
( )0 β V
2
0
arg 0
( ) t
ch e
seq k V V
C V
L T
−
⋅
⋅ =
β
β

Pipelining and Parallel Processing for Low Power (cont’d)
• Hence, we get the following equation to compute β:
• Once β is computed, the power consumption of the L-parallel system
can be calculated as
– Examples: Please see the examples (Example 3.4.2 and Example 3.4.3) in
the textbook (pp.77 and pp.80)
2
0
2
0 ( ) ( ) t t L β V − V = β V − V
para total seq P
L
P = LC V 2 f = 2 ⋅
0 ( )( β ) β

Pipelining and Parallel Processing for Low Power (cont’d)
Figures for Example 3.4.2
• A 4-tap FIR filter
• A 2-parallel filter
• An area-efficient 2-parallel filter
 


Pipelining and Parallel Processing for Low Power (cont’d)
• Combining Pipelining and Parallel Processing for Lower Power
– Pipelining and parallel processing can be combined for lower power
consumption: pipelining reduces the capacitance to be charged/discharged
in 1 clock period, while parallel processing increases the clock period for
charging/discharging the original capacitance
T
3T 3T
3T 3T
(a) 3T 3T
(b)
Figure: (a) Charge/discharge of entire capacitance in clock period T
(b) Charge/discharge of capacitance in clock period 3T using a
3-parallel 2-pipelined FIR filter

Pipelining and Parallel Processing for Low Power (cont’d)
– The propagation delay of the L-parallel M-pipelined filter is obtained as:
– Finally, we can obtain the following equation to compute β
– Example: please see the example in the textbook (pp.82)
( )
2
0
arg 0
2
0
arg 0
( ) ( ) t
ch e
t
ch e
pd k V V
L C V
k V V
C M V
LT
−
⋅ ⋅
=
−
⋅
=
β
β
2
0
2
0 ( ) ( ) t t LM ⋅ β V − V = β V − V


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